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MTV
2006
IEEE

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

14 years 8 days ago
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
Simulation-based validation of the current industrial processors typically use huge number of test programs generated at instruction set architecture (ISA) level. However, architectural test generation techniques have limitations in terms of exercising intricate micro-architectural artifacts. Therefore, it is necessary to use micro-architectural details during test generation. Furthermore, there is a lack of automated techniques for directed test generation targeting micro-architectural faults. To address these challenges, we present a directed test generation technique at micro-architectural level for functional validation of microprocessors. A processor model is described in a temporal specification language at micro-architecture level. The desired behaviors of micro-architecture mechanisms are expressed as temporal logic properties. We use decompositional model checking for systematic test generation. Our experiments using a processor based on the Power ArchitectureTM Technology1 ...
Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where MTV
Authors Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir
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