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DDECS
2006
IEEE

Dynamic Decimal Adder Circuit Design by using the Carry Lookahead

14 years 13 days ago
Dynamic Decimal Adder Circuit Design by using the Carry Lookahead
- This paper presents a carry lookahead (CLA) circuitry design based on dynamic circuit aiming at delay reduction in addition of BCD coded decimal numbers. The performance of the proposed dynamic decimal adder is analyzed demonstrating its speed improvement. Timing simulation on the proposed decimal addition circuit employing 0.25 CMOS technology yields the worst case delay of 622 .
Younggap You, Yong-Dae Kim, Jong Hwa Choi
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where DDECS
Authors Younggap You, Yong-Dae Kim, Jong Hwa Choi
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