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DAC
2000
ACM

Embedded hardware and software self-testing methodologies for processor cores

14 years 6 months ago
Embedded hardware and software self-testing methodologies for processor cores
At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardwarebased BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of selftest signatures. During the process of self-test, the test ...
Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar,
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2000
Where DAC
Authors Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng
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