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ISCAS
2003
IEEE

Fast prototyping of reconfigurable architectures from a C program

13 years 8 months ago
Fast prototyping of reconfigurable architectures from a C program
Rapid evaluation and design space exploration at the algorithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation methodology that targets reconfigurable architectures. Two main steps compose the estimation flow: i) the structural estimation which is technological independent and performs an automatic design space exploration and ii) the physical estimation which performs a technologic mapping to the target reconfigurable architecture. Experiments conducted on Xilinx (XC4000, Virtex) and Altera (Flex10K, Apex) components for a 2D DWT and a speech coder lead to an average error of about 10 % for temporal values and 18 % for area estimations.
Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISCAS
Authors Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet
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