Floating Point Unit Generation and Evaluation for FPGAs

Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generation approach outlined in this paper allows for the creation of a vast collection of floating point units with differing throughput, latency, and area characteristics. Given performance requirements, our generation tool automatically chooses the proper implementation algorithm and architecture to create a compliant floating point unit. Our approach is fully integrated into standard C++ using ASC, a stream compiler for FPGAs, and the PAM-Blox II module generation environment. The floating point units created by our approach exhibit a factor of two latency improvement versus commercial FPGA floating point units, while consuming only half of the FPGA logic area.

• Type: Conference
• Year: 2003
• Where: FCCM
• Authors: Jian Liang, Russell Tessier, Oskar Mencer
• Keywords: FCCM 2003, Hardware, Point Unit Generation, Possible floating Point, floating Point Units