Sciweavers

APCCAS
2006
IEEE

FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters

14 years 17 days ago
FPGA Prototyping of Spatio-temporal 2D IIR Broadband Beam Plane-wave Filters
— We propose a VLSI architecture for the single-chip realization of 2D spatio-temporal IIR digital filters, consisting of a meshed connection of concurrent identical vector-processors. The architecture is highly scalable, has high temporal throughput (80 MHz or more temporal frame samples/second, per sensor), and has excellent local interconnectivity. A single Xilinx Virtex-II xc2v2000 FPGA device circuit implementation is described for a highly selective first-order 2D infinite impulse response (IIR) broadband frequency-planar beam plane-wave filter, operating at a frame sample rate in excess of 80 MHz over a synchronously sampled linear sensor array consisting of 15 sensors and 15 A/D converters.
Arjuna Madanayake, Leonard T. Bruton
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where APCCAS
Authors Arjuna Madanayake, Leonard T. Bruton
Comments (0)