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DSD
2004
IEEE

Functional Validation of Programmable Architectures

13 years 9 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. Traditional validation techniques employ t reference models depending on the abstraction level and verification task (e.g., functional simulation or property checking), resulting in potential inconsistencies between multiple reference models. This paper presents a validation methodology that uses an Architecture Description Language (ADL) based specification as a golden reference model for validation of programmable architectures, and generation of executable models such as simulators and hardware prototypes. We present a validation framework that uses the generated hardware as a reference model to verify the hand-written implementation using a combination of symbolic simulation and equivalence checking. We als...
Prabhat Mishra, Nikil D. Dutt
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DSD
Authors Prabhat Mishra, Nikil D. Dutt
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