Sciweavers

DAC
2009
ACM

Generating test programs to cover pipeline interactions

14 years 6 months ago
Generating test programs to cover pipeline interactions
Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural specification driven methodology for systematic test-suite generation. Our primary contribution is an automated test-suite generation methodology that covers all possible processor pipeline interactions. To accomplish this automation, we (1) develop a fully formal processor model based on communicating extended finite state machines, and (2) traverse the processor model for on-the-fly generation of short test programs covering all reachable states and transitions. Our test generation method achieves several orders of magnitude reduction in test-suite size compared to the previously proposed formal approaches for test generation, leading to drastic reduction in validation effort. Categories and Subject Descriptors
Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra,
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2009
Where DAC
Authors Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra
Comments (0)