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ASIAMS
2008
IEEE

High-Performance Carry Select Adder Using Fast All-One Finding Logic

14 years 3 days ago
High-Performance Carry Select Adder Using Fast All-One Finding Logic
A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but with speed penalty. This paper proposes a new add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA, and no restrictions are imposed on the design of the adder blocks. For bit length n = 64, this new carry-select adders requires approximate 38 percent fewer transistors and16 percent shorter delay than the original dual ripple-carry carry-select adder.
Sun Yan, Zhang Xin, Jin Xi
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where ASIAMS
Authors Sun Yan, Zhang Xin, Jin Xi
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