Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

98

Voted

MAM
2006

92views more MAM 2006»

A high throughput 3D-bus interconnect for network processors

15 years 2 months ago

A high throughput 3D-bus interconnect for network processors

Download www.cs.ucf.edu

Deep layer processing and increasing line rates present a memory challenge to processor

Taskin Koçak, Jacob Engel

Real-time Traffic

Deep Layer Processing | Line Card | MAM 2006 | Memory Bandwidth |

claim paper

Related Content

» An areaefficient highthroughput hybrid interconnection network for singlechip parallel pro...

» A GALS manycore heterogeneous DSP platform with sourcesynchronous onchip interconnection n...

» Communication Centric Architectures for TurboDecoding on Embedded Multiprocessors

» A Pipelined Memory Architecture for High Throughput Network Processors

» Performance evaluation of wormhole routed network processormemory interconnects

» SplitRow A Reduced Complexity High Throughput LDPC Decoder Architecture

» NOC architecture design for multicluster chips

» Performance Evaluation of HighSpeed Interconnects Using Dense Communication Patterns

» The ClustRa Telecom Database High Availability High Throughput and RealTime Response

Post Info
More Details (n/a)

Added	14 Dec 2010
Updated	14 Dec 2010
Type	Journal
Year	2006
Where	MAM
Authors	Taskin Koçak, Jacob Engel

Comments (0)