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ASPDAC
2010
ACM

Improved on-chip router analytical power and area modeling

13 years 10 months ago
Improved on-chip router analytical power and area modeling
Over the course of this decade, uniprocessor chips have given way to multi-core chips which have become the primary building blocks of today's computer systems. The presence of multiple cores on a chip shifts the focus from computation to communication as a key bottleneck to achieving performance improvements. As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constraint, early-stage estimation of NoC power has become crucially important. Existing power models (e.g., ORION 2.0 [12], Xpipes [7], etc.) are based on certain router microarchitecture and circuit implementation. Therefore, when validated against different NoC prototypes - different router implementations
Andrew B. Kahng, Bill Lin, Kambiz Samadi
Added 10 Feb 2011
Updated 10 Feb 2011
Type Journal
Year 2010
Where ASPDAC
Authors Andrew B. Kahng, Bill Lin, Kambiz Samadi
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