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2008
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Leveraging on-chip networks for data cache migration in chip multiprocessors

13 years 10 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that remote, but on-chip, L2 cache accesses are less costly than off-chip accesses; this is in contrast to earlier chip-to-chip or board-to-board multiprocessors, where an access to a remote node is just as costly if not more so than a main memory access. This motivates on-chip cache migration as a means to retain more data on-chip. However, previously proposed techniques do not scale to high core counts: they do not leverage the on-chip caches of all cores nor have a scalable migration mechanism. In this paper we propose ascalable in-network migration technique which uses hints embedded within the router microarchitecture to steer L2 cache evictions towards free/invalid cache slots in any on-chip core cache, rather than evicting it offchip. We show that our technique can provide an average of a 19% reduction in ...
Noel Eisley, Li-Shiuan Peh, Li Shang
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where IEEEPACT
Authors Noel Eisley, Li-Shiuan Peh, Li Shang
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