Sciweavers

ISLPED
2003
ACM

Low cost instruction cache designs for tag comparison elimination

14 years 3 months ago
Low cost instruction cache designs for tag comparison elimination
Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comparisons that can be removed. For this purpose, two low cost innovations are proposed in this paper. We design a small dedicated TCE table whose size is flexible both horizontally (entry size) and vertically (number of entries). The design also minimizes interactions with the I-cache. For a 64-way 16K cache, the new design reduces the tag comparisons to 4.0% with a fraction only 20% of the hardware costof the way memoization technique [5]. The result is 40% better compared to a recent proposed low cost design [2] of comparable hardware cost. Categoriesand Subject Descriptors General Terms Keywords B.3.2 [MemoryStructures] Design Tag Comparison Elimination,Low-Power Instruction Cache
Youtao Zhang, Jun Yang 0002
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where ISLPED
Authors Youtao Zhang, Jun Yang 0002
Comments (0)