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ISCAS
2006
IEEE

Low power state-parallel relaxed adaptive Viterbi decoder design and implementation

14 years 11 days ago
Low power state-parallel relaxed adaptive Viterbi decoder design and implementation
Abstract— In this paper, we present an algorithm/architecturelevel design solution for implementing state-parallel adaptive Viterbi decoders that, compared with their Viterbi counterparts, can achieve significant power savings and modest silicon area reduction, while maintaining almost the same decoding performance and throughput. The effectiveness of the proposed solution has been demonstrated using convolutional codes decoders as test vehicles, where Synopsys tools are used for synthesis, layout, and post-layout power estimation.
Fei Sun, Tong Zhang
Added 12 Jun 2010
Updated 12 Jun 2010
Type Conference
Year 2006
Where ISCAS
Authors Fei Sun, Tong Zhang
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