Massively parallel processing on a chip

13 years 6 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution of the famous massively parallel systems proposed at the end of the eighties. We claim that today such a machine may be integrated in a single chip. On one side, new design methodologies such as IP reuse and, on the other side, the possible high level of integration on a chip let us envisage such a revival. Some improvements of the system architecture are possible because of the high degree of integration: The mppSoC processing elements share most of their design with the control processor, the integrated network allows to exchange data between PEs, but also between the control processor and the PE memories, and even to connect the external devices to the system. This paper presents the mppSoC architecture, a cycleaccurate bit-accurate SystemC simulator of this architecture, and a prototype of implementation ...
Philippe Marquet, Simon Duquennoy, Sébastie
Added 12 Aug 2010
Updated 12 Aug 2010
Type Conference
Year 2007
Where CF
Authors Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser
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