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CODES
2011
IEEE

Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends

12 years 3 months ago
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends
Designing memory controllers for complex real-time and highperformance multi-processor systems-on-chip is challenging, since sufficient capacity and (real-time) performance must be provided in a reliable manner at low cost and with low power consumption. This special session contains four presentations that describe these challenges and proposed solutions for DRAM and flash memory controllers, respectively. The first presentation discusses performance and reliability issues in flash memories, while the second identifies challenges in providing DRAM access to memory clients with mixed time-criticality. The third presentation proposes an integrated approach to optimize cost and performance of the DRAM subsystem, and the last one describes how wide DRAM interfaces enabled by 3D technology improve DRAM performance and reduces power. Categories and Subject Descriptors: B.8.2 [Performance and reliability]: Performance Analysis and Design Aids General Terms: Design, Performance, Reliabil...
Benny Akesson, Po-Chun Huang, Fabien Clermidy, Den
Added 18 Dec 2011
Updated 18 Dec 2011
Type Journal
Year 2011
Where CODES
Authors Benny Akesson, Po-Chun Huang, Fabien Clermidy, Denis Dutoit, Kees Goossens, Yuan-Hao Chang, Tei-Wei Kuo, Pascal Vivet, Drew Wingard
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