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ASPDAC
2010
ACM

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Minimizing clock latency range in robust clock tree synthesis

15 years 4 days ago

Minimizing clock latency range in robust clock tree synthesis

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Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen

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Added	28 Feb 2011
Updated	28 Feb 2011
Type	Journal
Year	2010
Where	ASPDAC
Authors	Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen

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