Modeling a system controller for timing analysis

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Modeling a system controller for timing analysis
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the execution history sensitive behavior of components like caches, pipelines, buffers and periphery, the static determination of safe upper execution-time bounds is a challenging task. A successful timing analysis approach developed at Saarversity/AbsInt GmbH uses abstract interpretation to derive safe WCET bounds based on timing models of the processor and periphery in a system. So far, WCET research has focused on processor timing behavior. System performance depends heavily on the performance of the periphery, namely the system controller, which includes the memory access logic. This paper is the first to describe experience in deriving a timing model for such a system controller. The starting point is the VHDL description from which the controllers FPGA implementation is synthesized. uence of simplifications ...
Stephan Thesing
Added 22 Aug 2010
Updated 22 Aug 2010
Type Conference
Year 2006
Authors Stephan Thesing
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