Noise considerations in circuit optimization

13 years 4 months ago
Noise considerations in circuit optimization
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is particularly susceptible to charge-sharing and coupling noise. Thus the design and optimization of a circuit should take noise considerations into account. Such considerations are typically stated as semi-in nite constraints. In addition, the number of signals to be checked and the number of sub-intervals of time during which the checking must be performed can potentially be very large. Thus, the practical incorporation of noise constraints during circuit optimization is a hitherto unsolved problem. This paper describes a novel method for incorporating noise considerations during automatic circuit optimization. Semi-in nite constraints representing noise considerations are rst converted to ordinary equality constraints involving time integrals, which are readily computed in the context of circuit optimization based...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1998
Authors Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah
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