Sciweavers

RTCSA
1999
IEEE

Pipeline Timing Analysis Using a Trace-Driven Simulator

14 years 2 months ago
Pipeline Timing Analysis Using a Trace-Driven Simulator
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipeline modeling. Our technique handle CPUs that execute multiple shorter instructions in parallel with long-running instructions. The results of other machine analyses, like cache analysis, can be used in our pipeline analysis. Also, results from high-level program ow analysis can be used to tighten the execution time predictions. Our primary target is embedded real-time systems, and since processor simulators are standard equipment for embedded development work, our tool will be easy to port to relevant target processors.
Jakob Engblom, Andreas Ermedahl
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1999
Where RTCSA
Authors Jakob Engblom, Andreas Ermedahl
Comments (0)