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2008
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Place-and-Route Impact on the Security of DPL Designs in FPGAs

13 years 9 months ago
Place-and-Route Impact on the Security of DPL Designs in FPGAs
—Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak points of the electronic devices which implement it. These attacks, known as side-channel attacks, have proved to be very powerful in retrieving secret keys from any kind of unprotected electronic device. Amongst the various protection strategies, side-channel hiding is very popular and well studied. The principle of information hiding is to make any leak constant, thus uncorrelated to the device internal secrets. The so-called “dual-rail with precharge logic” (DPL) style is indicated to achieve that goal. For DPL protection to be effective, it further requires a carefully balanced layout so as to obtain equal propagation delays and power consumption on both rails. In this article, we study to which extent the differential place-and-route constraints must be strict in FPGA technology. We describe placement ...
Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Dange
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where HOST
Authors Sylvain Guilley, Sumanta Chaudhuri, Jean-Luc Danger, Laurent Sauvage, Philippe Hoogvorst, Maxime Nassar, Tarik Graba, Vinh-Nga Vong
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