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ASAP
2005
IEEE

Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application

13 years 11 months ago
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
Users expect future handhelddevices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and power consumption and forces designers to optimize all parts of their platform. Evaluating the overall platform power breakdown is therefore critical to determine where to spend the efforts on power optimization. Surprisingly, few studies exist on that topic and decisions generally rely on common belief. We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks. This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from camera to display. Our power breakdown identifies the main bottlenecks in the memory hierarchy and the foreground memory, and shows that global interconnect is not that critical for a well-optimized a...
Andy Lambrechts, Praveen Raghavan, Anthony Leroy,
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where ASAP
Authors Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina
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