gn process of embedded systems moves currently towards higher levels of abstraction. As a consequence, a need arises for an early and realistic assessment of system level design decisions. In order to provide the early access, an automatic generation of its simulation models is advocated. While Verilog and VHDL are being extended in order to improve their system-level capabilities, SystemC community is intensively extending SystemC to software modeling features. In this sense, SystemC support for a realistic assessment of embedded system in the process of develop-validate-and-test its software is advocated. This step is done before any decisions with respect to processor and operating system has been finalized, as well as before an executable platform model and prototype board becomes available. Moreover, while execution properties of embedded software processes, which more and more dominate the functionality of embedded systems, can considerably vary both due to processor pipeline an...
P. Hastono, Stephan Klaus, Sorin A. Huss