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FPGA
2000
ACM

A reconfigurable multi-function computing cache architecture

13 years 9 months ago
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially the computing bandwidth limited applications. Instead, such applications may be able to use some additional computing resources. If the unused portion of the cache could serve these computation needs, the on-chip resources would be utilized more efficiently. This presents an opportunity to explore the reconfiguration of a part of the cache memory for computing. In this paper, we present a cache architecture to convert a cache into a computing unit for either of the following two structured computations, FIR and DCT/IDCT. In order to convert a cache memory to a function unit, we include additional logic to embed multibit output LUTs into the cache structure. Therefore, the cache can perform computations when it is reconfigured as a function unit. The experimental results show that the reconfigurable module im...
Huesung Kim, Arun K. Somani, Akhilesh Tyagi
Added 24 Aug 2010
Updated 24 Aug 2010
Type Conference
Year 2000
Where FPGA
Authors Huesung Kim, Arun K. Somani, Akhilesh Tyagi
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