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ICCAD
2007
IEEE

A selective pattern-compression scheme for power and test-data reduction

14 years 9 months ago
A selective pattern-compression scheme for power and test-data reduction
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supply the test patterns either through the compressed scan chain whose scanned values will be decoded to the original scan cells, or directly through the original scan chain using minimum transition filling method. Due to shorter length of a compressed scan chain, the potential switching activities and the required storage bits can be both reduced. Furthermore, the proposed scheme also supports multiple scan chains. The experimental results demonstrate that, with few hardware overhead, the proposed scheme can achieve significant improvement in shift-in power reduction and large amount of test data volume reduction.
Chia-Yi Lin, Hung-Ming Chen
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2007
Where ICCAD
Authors Chia-Yi Lin, Hung-Ming Chen
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