Software Managed Distributed Memories in MPPAs

When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms for building logically larger memories, it often requires developer intervention on word-oriented devices like Massively Parallel Processor Arrays (MPPAs). We examine building larger memories on the Ambric MPPA. Building an efficient structure requires low-level development and analysis of latency and bandwidth effects of network and protocol choices. We build a network that only requires only five instructions per transaction after optimization. The resource use and performance suggests architectural enhancements that should be considered for future devices. Keywords-MPPA; memory; pipelining;

• Type: Journal
• Year: 2010
• Where: FPL
• Authors: Robin Panda, Jimmy Xu, Scott Hauck
• Keywords: FPL 2010, Hardware, Larger Memories, Reconfigurable Hardware, Single Hardware Block