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HPCA
2012
IEEE

Staged Reads: Mitigating the impact of DRAM writes on DRAM reads

11 years 10 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However, writes must be eventually processed and they often delay pending reads. In fact, a single channel in the main memory system offers almost no parallelism between reads and writes. This is because a single off-chip memory bus is shared by reads and writes and the direction of the bus has to be explicitly turned around when switching from writes to reads. This is an expensive operation and its cost is amortized by carrying out a burst of writes or reads every time the bus direction is switched. As a result, no reads can be processed while a memory channel is busy servicing writes. This paper proposes a novel mechanism to boost read-write parallelism and perform useful components of read operations even when the memory system is busy performing writes. If some of the banks are busy servicing writes, we start is...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev
Added 24 Apr 2012
Updated 24 Apr 2012
Type Journal
Year 2012
Where HPCA
Authors Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
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