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IPPS
2003
IEEE

System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC

13 years 7 months ago
System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC
To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects in to a design flow. They all lack either an interface to commercially available and industrially used tools or are restricted to a single vendor or technology environment. Therefore a methodology for modeling of dynamically re-configurable blocks at the system-level using SystemC 2.0 is presented. The high-level model is based on a multi-context representation of the different functionalities that will be mapped on the re-configurable block during different run-time periods. By specifying the estimated times of context-switching and active-running in the selected functionality modes, the methodology allows to do true design space exploration at the system-level, without the need to map the design first to an actual technology implementation....
Antti Pelkonen, Kostas Masselos, Miroslav Cup&aacu
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where IPPS
Authors Antti Pelkonen, Kostas Masselos, Miroslav Cupák
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