Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits

Gate oxide tunneling current (Igate) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce Igate is to leverage dual Tox processes where non-critical transistors are assigned a thicker Tox. In this paper, we generate a leakage/delay tradeoff curve for dual Tox circuits, and propose a transistor and pin reordering technique that has a minimal layout impact to further reduce the total leakage current up to 18% and Igate up to 26% without incurring any delay penalty.

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar
• Keywords: Dual Tox Circuits, Hardware, ICCD 2004, Leverage Dual Tox, Thicker Tox