Sciweavers

ASPDAC
2005
ACM

Wire congestion and thermal aware 3D global placement

14 years 2 days ago
Wire congestion and thermal aware 3D global placement
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated due to the compact nature of these layered technologies. In this paper, we develop techniques to reduce the maximum temperature and wire congestion of 3D circuits without compromising total wirelength and via count. Our approach consists of two phases. First, we use a multi-level min-cut placement with a modified gain function for local wire congestion and dynamic power consumption reduction. Second, we perform simulated annealing together with full-length thermal analysis and global routing for global wire congestion and maximum temperature reduction. Our experimental results show smooth tradeoff among congestion, temperature, wirelength, and via.
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwa
Added 26 Jun 2010
Updated 26 Jun 2010
Type Conference
Year 2005
Where ASPDAC
Authors Karthik Balakrishnan, Vidit Nanda, Siddharth Easwar, Sung Kyu Lim
Comments (0)