Wire type assignment for FPGA routing

14 years 18 days ago
Wire type assignment for FPGA routing
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently developed FPGAs (e.g., Virtex-II), there are more versatile wire types and richer connections between them than those of the older generations of FPGAs (e.g. XC4000). To fully exploit the potential of the new routing architectures, it is beneficial to perform wire type assignment for all channels as an intermediate stage between global routing and detailed routing. In this paper, we present a wire-type assignment algorithm that is based on iteratively applying min-cost maxflow technique to simultaneously route many nets. At each stage of the network flow computation, we have guaranteed optimal result in terms of routability and delay cost. We use the routing architecture of the Virtex-II FPGAs from Xilinx as a target architecture in our experiments. Experimental results show that our algorithm outperforms the...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
Added 06 Jul 2010
Updated 06 Jul 2010
Type Conference
Year 2003
Where FPGA
Authors Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
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