Application specific instruction-set processors combine an efficient general purpose core with special purpose functionality that is tailored to a particular application domain. ...
Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael ...
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
We introduce a novel multi-resource allocator to dynamically allocate resources for database servers running on virtual storage. Multi-resource allocation involves proportioning t...
Gokul Soundararajan, Daniel Lupei, Saeed Ghanbari,...
— Implementing shared memory consistency models on top of hardware caches gives rise to the well-known cache coherence problem. The standard solution involves implementing cohere...
: Topic Modeling Ensembles Zhiyong Shen, Ping Luo, Shengwen Yang, Xukun Shen HP Laboratories HPL-2010-158 Topic model, Ensemble In this paper we propose a framework of topic model...