186 search results - page 3 / 38 » 1995 high level synthesis design repository |
DAC
2001
ACM
14 years 7 months ago
2001
ACM
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow through conditions and loops in the input description. In...
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...
ISQED
2007
IEEE
14 years 16 days ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...
DATE
2003
IEEE
13 years 11 months ago
2003
IEEE
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branche...
FDL
2007
IEEE
14 years 18 days ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...