34 search results - page 3 / 7 » 3D floorplanning with thermal vias |
ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— Thermal issues are a primary concern in the threedimensional (3D) integrated circuit (IC) design. Temperature, area, and wire length must be simultaneously optimized du...
67
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ICCD
2007
IEEE
15 years 6 months ago
2007
IEEE
One of the biggest challenges in 3D stacked IC design is heat dissipation. Incorporating thermal vias is a promising method for reducing the temperatures of 3D ICs. The bonding st...
ISLPED
2006
ACM
15 years 3 months ago
2006
ACM
All existing methods for thermal-via allocation are based on a steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and ...
131
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MJ
2011
14 years 4 months ago
2011
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...