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» 3D floorplanning with thermal vias
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124
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TPDS
2010
109views more  TPDS 2010»
15 years 6 days ago
Thermal-Aware Task Scheduling for 3D Multicore Processors
Abstract—A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, highspeed interface to increase the device den...
Xiuyi Zhou, Jun Yang 0002, Yi Xu, Youtao Zhang, Ji...
129
Voted
DAC
2007
ACM
16 years 2 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar
NANONET
2009
Springer
199views Chemistry» more  NANONET 2009»
15 years 6 months ago
Through Silicon Via-Based Grid for Thermal Control in 3D Chips
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between...
José L. Ayala, Arvind Sridhar, Vinod Pangra...
ASPDAC
2007
ACM
164views Hardware» more  ASPDAC 2007»
15 years 5 months ago
Thermal-Aware 3D IC Placement Via Transformation
- 3D IC technologies can help to improve circuit performance and lower power consumption by reducing wirelength. Also, 3D IC technology can be used to realize heterogeneous system-...
Jason Cong, Guojie Luo, Jie Wei, Yan Zhang
126
Voted
ICPP
2008
IEEE
15 years 8 months ago
Thermal Management for 3D Processors via Task Scheduling
A rising horizon in chip fabrication is the 3D integration technology. It stacks two or more dies vertically with a dense, high-speed interface to increase the device density and ...
Xiuyi Zhou, Yi Xu, Yu Du, Youtao Zhang, Jun Yang 0...