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CODES
1999
IEEE
15 years 4 months ago
Power estimation for architectural exploration of HW/SW communication on system-level buses
The power consumption due to the HW/SW communication on system-level buses represents one of the major contributions to the overall power budget. A model to estimate the switching...
William Fornaciari, Donatella Sciuto, Cristina Sil...
USENIX
1993
15 years 1 months ago
Exploiting In-Kernel Data Paths to Improve I/O Throughput and CPU Availability
We present the motivation, design, implementation, and performance evaluation of a UNIX kernel mechanism capable of establishing fast in-kernel data pathways between I/O objects. ...
Kevin R. Fall, Joseph Pasquale
CHI
2007
ACM
16 years 3 days ago
ExperiScope: an analysis tool for interaction data
We present ExperiScope, an analytical tool to help designers and experimenters explore the results of quantitative evaluations of interaction techniques. ExperiScope combines a ne...
François Guimbretière, Ken Hinckley,...
HPCA
1998
IEEE
15 years 4 months ago
The Impact of Data Transfer and Buffering Alternatives on Network Interface Design
The explosive growth in the performance of microprocessors and networks has created a new opportunity to reduce the latency of fine-grain communication. Microprocessor clock speed...
Shubhendu S. Mukherjee, Mark D. Hill
SLIP
2003
ACM
15 years 5 months ago
Error-correction and crosstalk avoidance in DSM busses
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
Ketan N. Patel, Igor L. Markov