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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
15 years 1 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
TOG
2002
112views more  TOG 2002»
14 years 9 months ago
Ray tracing on programmable graphics hardware
Recently a breakthrough has occurred in graphics hardware: fixed function pipelines have been replaced with programmable vertex and fragment processors. In the near future, the gr...
Timothy J. Purcell, Ian Buck, William R. Mark, Pat...
HPCA
1999
IEEE
15 years 1 months ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...
SIGOPS
2011
215views Hardware» more  SIGOPS 2011»
14 years 4 months ago
Log-based architectures: using multicore to help software behave correctly
While application performance and power-efficiency are both important, application correctness is even more important. In other words, if the application is misbehaving, it is li...
Shimin Chen, Phillip B. Gibbons, Michael Kozuch, T...
EUROPAR
2009
Springer
15 years 4 months ago
A Multilevel Parallelization Framework for High-Order Stencil Computations
Stencil based computation on structured grids is a common kernel to broad scientific applications. The order of stencils increases with the required precision, and it is a challeng...
Hikmet Dursun, Ken-ichi Nomura, Liu Peng, Richard ...