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HIPEAC
2011
Springer
13 years 9 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
JMLR
2011
117views more  JMLR 2011»
14 years 4 months ago
Parameter Screening and Optimisation for ILP using Designed Experiments
Reports of experiments conducted with an Inductive Logic Programming system rarely describe how specific values of parameters of the system are arrived at when constructing model...
Ashwin Srinivasan, Ganesh Ramakrishnan
TCSV
2010
14 years 4 months ago
High Performance Stereo Vision Designed for Massively Data Parallel Platforms
Abstract--Real-time stereo vision is attractive in many applications like robot navigation and 3D scene reconstruction. Data parallel platforms, e.g. GPU, is often used for real-ti...
Wei Yu, Tsuhan Chen, Franz Franchetti, James C. Ho...
RTAS
2006
IEEE
15 years 3 months ago
Switch Scheduling and Network Design for Real-Time Systems
The rapid need for high bandwidth and low latency communication in distributed real-time systems is driving system architects towards high-speed switches developed for high volume...
Sathish Gopalakrishnan, Marco Caccamo, Lui Sha
MEDES
2009
ACM
15 years 4 months ago
A web-based interface to design information visualization
Information Visualization is a challenging field, enabling a better use of humans’ visual and cognitive system, to make sense of very large datasets. This paper aims at improvi...
Romain Vuillemot, Béatrice Rumpler