54 search results - page 5 / 11 » A Bus Delay Reduction Technique Considering Crosstalk |
101
Voted
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems bei...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
101
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ISPD
2005
ACM
15 years 3 months ago
2005
ACM
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
107
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GLVLSI
2006
IEEE
15 years 3 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
- Traditionally, minimum possible area of a VLSI layout is considered the best for delay and power minimization due to decreased interconnect capacitance. This paper shows however ...