54 search results - page 6 / 11 » A Bus Delay Reduction Technique Considering Crosstalk |
89
Voted
DAC
2003
ACM
15 years 2 months ago
2003
ACM
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
ISPASS
2006
IEEE
15 years 3 months ago
2006
IEEE
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
86
Voted
RTAS
2002
IEEE
15 years 2 months ago
2002
IEEE
Delay variations (jitter) in computations and communications cause degradation of performance in control applications. There are many sources of jitter, including variations in ex...
67
Voted
VLSID
2000
IEEE
15 years 1 months ago
2000
IEEE
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each...