Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensate...
To use their pool of resources efficiently, distributed stream-processing systems push query operators to nodes within the network. Currently, these operators, ranging from simple...
Peter R. Pietzuch, Jonathan Ledlie, Jeffrey Shneid...
Preserving digital information over the long term becomes increasing important for large number of institutions. The required expertise and limited tool support discourage especial...
Stephan Strodl, Petar Petrov, Michael Greifeneder,...
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
Abstract The ntcc process calculus is a timed concurrent constraint programming (ccp) model equipped with a first-order linear-temporal logic (LTL) for expressing process specifi...