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» A Case for MLP-Aware Cache Replacement
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RTAS
1996
IEEE
15 years 1 months ago
Efficient worst case timing analysis of data caching
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
HIPC
1999
Springer
15 years 1 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
DAC
2012
ACM
12 years 12 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
SODA
1994
ACM
88views Algorithms» more  SODA 1994»
14 years 10 months ago
Optimal Prediction for Prefetching in the Worst Case
Response time delays caused by I/O are a major problem in many systems and database applications. Prefetching and cache replacement methods are attracting renewed attention because...
P. Krishnan, Jeffrey Scott Vitter
CASES
2001
ACM
15 years 1 months ago
Transparent data-memory organizations for digital signal processors
Today's digital signal processors (DSPs), unlike general-purpose processors, use a non-uniform addressing model in which the primary components of the memory system--the DRAM...
Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob