45 search results - page 7 / 9 » A Case for MLP-Aware Cache Replacement |
CSREAESA
2006
15 years 1 months ago
2006
Modern processors have a small on-chip local memory for instructions. Usually it is in the form of a cache but in some cases it is an addressable memory. In the latter, the user is...
STOC
2006
ACM
15 years 5 months ago
2006
ACM
Memory management is a fundamental problem in computer architecture and operating systems. We consider a two-level memory system with fast, but small cache and slow, but large mai...
105
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CASES
2003
ACM
15 years 4 months ago
2003
ACM
This paper presents a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-m...
110
click to vote
LCTRTS
2007
Springer
15 years 5 months ago
2007
Springer
As mobile phones become increasingly multifunctional, the number and size of applications installed in phones are rapidly increasing. Consequently, mobile phones require more hard...
114
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IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...