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ECRTS
2009
IEEE
14 years 7 months ago
Precise Worst-Case Execution Time Analysis for Processors with Timing Anomalies
This paper explores timing anomalies in WCET analysis. Timing anomalies add to the complexity of WCET analysis and make it hard to apply divide-and-conquer strategies to simplify ...
Raimund Kirner, Albrecht Kadlec, Peter P. Puschner
WSC
2004
14 years 11 months ago
A Case Study in Meta-Simulation Design and Performance Analysis for Large-Scale Networks
Simulation and Emulation techniques are fundamental to aid the process of large-scale protocol design and network operations. However, the results from these techniques are often ...
David W. Bauer, Garrett R. Yaun, Christopher D. Ca...
CODES
2004
IEEE
15 years 1 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
DSD
2011
IEEE
194views Hardware» more  DSD 2011»
13 years 9 months ago
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of wel...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
ASAP
2010
IEEE
185views Hardware» more  ASAP 2010»
14 years 9 months ago
ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processors
Abstract—The demand for biomedical implants keeps increasing. However, most of the current implant design methodologies involve custom-ASIC design. The SiMS project aims to chang...
Dhara Dave, Christos Strydis, Georgi Gaydadjiev