15 search results - page 2 / 3 » A Circuit Level Fault Model for Resistive Opens and Bridges |
VTS
2005
IEEE
14 years 5 hour ago
2005
IEEE
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...
GLVLSI
2002
IEEE
13 years 11 months ago
2002
IEEE
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
DATE
2002
IEEE
13 years 11 months ago
2002
IEEE
In this work, the problem of open faults affecting the interconnections of SC circuits composed by data-path and control is analyzed. In particular, it is shown that, in case open...
DAC
2000
ACM
13 years 10 months ago
2000
ACM
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
DFT
2003
IEEE
13 years 11 months ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...