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HPCA
2008
IEEE
14 years 6 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
ICPP
2005
IEEE
13 years 12 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
INTERSENSE
2006
ACM
14 years 6 days ago
QoS-aware mesh construction to enhance multicast routing in mobile ad hoc networks
— Mobile Ad-hoc Networks (MANETs) are seen as an essential technology to support future Pervasive Computing Scenarios and 4G networks. In a MANET, efficient support of multipoint...
Harald Tebbe, Andreas J. Kassler, Pedro M. Ruiz
MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
13 years 4 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
ICC
2007
IEEE
165views Communications» more  ICC 2007»
14 years 17 days ago
Threshold-based Exhaustive Round-Robin for the CICQ Switch with Virtual Crosspoint Queues
A multi-cabinet implementation of a combined input and crosspoint queued (CICQ) switch introduces a large RTT latency between the line cards and switch fabric, requiring a large cr...
Kenji Yoshigoe