70 search results - page 7 / 14 » A Compact Transactional Memory Multiprocessor System on FPGA |
DAC
2008
ACM
15 years 10 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...
FPGA
1995
ACM
15 years 1 months ago
1995
ACM
The future Large Hadron Collider (LHC) to be built at CERN1, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here...
IPPS
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
82
Voted
EUROSYS
2007
ACM
15 years 6 months ago
2007
ACM
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
77
Voted
PDP
2006
IEEE
15 years 3 months ago
2006
IEEE
Commodity symmetric multiprocessors (SMPs), though originally intended for transaction processing, because of their availability, are now used for numerical analysis applications ...