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» A Compact Transactional Memory Multiprocessor System on FPGA
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ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 2 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
JSA
2007
162views more  JSA 2007»
14 years 9 months ago
Exploration of distributed shared memory architectures for NoC-based multiprocessors
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric inter...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
HPCA
2006
IEEE
15 years 9 months ago
LogTM: log-based transactional memory
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan...
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HPCA
2003
IEEE
15 years 9 months ago
Memory System Behavior of Java-Based Middleware
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...
Martin Karlsson, Kevin E. Moore, Erik Hagersten, D...
TPDS
2010
260views more  TPDS 2010»
14 years 7 months ago
Real-Time Modeling of Wheel-Rail Contact Laws with System-On-Chip
—This paper presents the development and implementation of a multiprocessor system-on-chip solution for fast and real time simulations of complex and nonlinear wheel-rail contact...
Yongji Zhou, T. X. Mei, Steven Freear