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» A Comparison of Two Architectural Power Models
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CAL
2008
14 years 9 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
ISCAPDCS
2008
14 years 11 months ago
Parallel Embedded Systems: Where Real-Time and Low-Power Meet
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...
Zdravko Karakehayov, Yu Guo
ECCC
2000
158views more  ECCC 2000»
14 years 9 months ago
On the Computational Power of Winner-Take-All
This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve ...
Wolfgang Maass
BMCBI
2011
14 years 1 months ago
Software comparison for evaluating genomic copy number variation for Affymetrix 6.0 SNP array platform
Background: Copy number data are routinely being extracted from genome-wide association study chips using a variety of software. We empirically evaluated and compared four freely-...
Jeanette E. Eckel-Passow, Elizabeth J. Atkinson, S...
79
Voted
ICSE
1998
IEEE-ACM
15 years 1 months ago
Integrating Architecture Description Languages with a Standard Design Method
Software architecture descriptions are high-level models of software systems. Some researchers have proposed specialpurpose architectural notations that have a great deal of expre...
Jason E. Robbins, Nenad Medvidovic, David F. Redmi...