285 search results - page 22 / 57 » A Comparison of Two Architectural Power Models |
ISCA
2010
IEEE
15 years 2 months ago
2010
IEEE
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
VLSID
2006
IEEE
15 years 9 months ago
2006
IEEE
Serial links in network on chip provide advantages in terms of reduced wiring area, reduced switch complexity and power. However, serial links offer lower bandwidth in comparison ...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based...
114
Voted
MOBIHOC
2005
ACM
15 years 9 months ago
2005
ACM
We consider a wireless sensor network in which sensors are grouped into clusters, each with its own cluster head (CH). Each CH collects data from sensors in its cluster and relays...